Riverlane is seeking a Verification Engineer in Cambridge to own end-to-end verification and drive the quality of our hardware and embedded software stacks. You will design scalable testbenches using SystemVerilog, implement checkers, and develop reference models to ensure robust, reliable systems.
Collaboration with designers will be essential to define plans and improve coverage. You will work across block- and system-level designs, maintain the verification environment, and track regressions
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Join us at Riverlane as our next End-to-End Verification Engineer - SystemVerilog in Cambridge, England, United Kingdom.
This opportunity is part of our work in Engineering.
The advertised compensation is 55.000 - 75.000.
We aim to respond to suitable candidates as soon as possible.
Full responsibilities and requirements are described in the listing above.
Learn more about the End-to-End Verification Engineer - SystemVerilog role in the description above.