Intellectual Capital Resources Ltd. is seeking Design Verification Engineers to join a growing semiconductor group in Edinburgh.
You will contribute to digital verification for complete mixed-signal ICs, build advanced verification environments, and help improve methodologies across projects. This role offers a flat culture, strong development opportunities, and a competitive compensation package including RSUs.
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Our group is growing, and we are hiring a Hybrid Design Verification Engineer (SystemVerilog/UVM) in City of Edinburgh, Scotland, United Kingdom.
Join Intellectual Capital Resources Ltd and contribute to our ongoing work.
Take a moment to read everything above and see whether this role is right for you.
This posting is for the Hybrid Design Verification Engineer (SystemVerilog/UVM) role at Intellectual Capital Resources Ltd, based in City of Edinburgh, Scotland, United Kingdom.
We are looking to fill the Hybrid Design Verification Engineer (SystemVerilog/UVM) position at Intellectual Capital Resources Ltd in City of Edinburgh, Scotland, United Kingdom.