SmartEdge, Lda is seeking experienced SoC Design Verification Engineers to verify a next-generation multi-die SoC. You will perform subsystem and SoC-level verification using SystemVerilog/UVM, and develop processor-based C tests for embedded cores.
Ideal candidates have strong debugging skills, understand ARM-based SoC architectures, and can adapt existing verification environments to evolving design requirements while contributing to regression planning and coverage closure.
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Step into the SoC DV Engineer: SystemVerilog/UVM & Embedded C Verification role at SmartEdge, Lda in West of England, England, United Kingdom and grow with us.
This is a strong opening to take on the SoC DV Engineer: SystemVerilog/UVM & Embedded C Verification role at SmartEdge, Lda.
As a SoC DV Engineer: SystemVerilog/UVM & Embedded C Verification, you will play an important part at SmartEdge, Lda in West of England, England, United Kingdom.