Salience Labs Ltd. is seeking a Physical Verification Engineer to drive DRC/LVS signoff for IC and photonic IC designs.
You will work at the intersection of electronic and photonic design, validating layouts and ensuring tapeout cleanliness. The role requires 3+ years of hands-on physical verification experience, proficiency with Calibre or Synopsys ICV for DRC/LVS signoff, GDS/OASIS knowledge, and strong scripting skills in Python/Tcl/Shell.
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Step into the IC & PIC Physical Verification Engineer — Tapeout Ready role at Salience Labs Ltd in Oxford, England, United Kingdom and grow with us.
We aim to respond to suitable candidates as soon as possible.
Full responsibilities and requirements are described in the listing above.
Learn more about the IC & PIC Physical Verification Engineer — Tapeout Ready role in the description above.
We appreciate your interest in this position.