Graphcore in Bristol, UK is seeking a Hardware Validation & Debug Engineer to validate memory subsystems and system interfaces for next‑generation AI compute platforms. You will own lab validation, investigate failures, tune LPDDR memory (incl.
LPDDR5), and coordinate root‑cause analysis with hardware and firmware teams. You will work with Architecture, Silicon, Firmware, PCB design and power teams to translate lab findings into actionable fixes, reporting progress with clear debugging
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For the DDR Hardware Validation & Debug Engineer position at Graphcore, we are reviewing applications now.
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This posting is for the DDR Hardware Validation & Debug Engineer role at Graphcore, based in West of England, England, United Kingdom.