Staff Verification Engineer at Riverlane, Cambridge, UK. A lead-level full time position in the Engineering team, listed under software engineering.
The salary range for this role is broad, as we are able to consider varying levels of experience. Any offer made will carefully take into account level of experience (including relevant industry experience), transferable relevant skills and previous relevant achievements.
We will also consider part-time applications for this role. Please indicate your preferred working schedule in your cover letter.
About the role
As a Staff Verification Engineer at Riverlane, you will take ownership of verification across block, subsystem, and multi-FPGA system-level designs. Collaborating closely with hardware designers and embedded software engineers, you will deliver systems that are fully verified, high-performing, and trusted.
With visibility across the entire stack, you will partner closely with the Lead Verification Engineer to define and deliver the verification strategy - from early design discussions through to full system-level validation - ensuring every part of our technology meets the highest standards of performance and reliability.
You do not need a background in quantum computing! You will learn this along the way.
What we need
Strong hands‑on expertise in SystemVerilog and UVM.
What can you expect from us
- A comprehensive benefits package that includes an annual bonus plan, private medical insurance, life insurance, and a contributory pension scheme
- Equity, so that our team can share in the long‑term success of Riverlane
Responsibilities
- Own the strategy and execution for block‑level, subsystem, and multi‑FPGA system designs.
- Develop scalable UVM‑based testbenches that push the boundaries of performance across multiple FPGAs and configurations, ensuring our systems behave flawlessly in real‑world conditions.
- Drive verification efforts with a sharp focus on risk, coverage, and system-level behaviour, setting the bar for quality and establishing best practices that elevate the wider team.
- Make pragmatic trade‑offs to maintain world‑class quality, while keeping pace with innovation, directly shaping the reliability and impact of Riverlane’s cutting‑edge technology.
Requirements
- Proven ability to debug across RTL, simulation, and hardware.
- Ability to work effectively with ambiguity and changing requirements.
- Demonstrable commercial experience in functional verification, including ownership of verification planning and strategy.
- Exposure to different programming languages, such as C, C++ and Python.
- A proactive person who can independently define the scope of work.
- A collaborative person with excellent communication skills, who actively shares (and listens to) constructive feedback.
- Experience mentoring junior verification engineers.
Nice to Have
- A diverse work environment that brings together experts in many fields (including software and hardware development, quantum information theory, physics and maths) and over 20 different nationalities
- A learning environment that encourages individual, team and company growth and development, including a regular programme of learning events and training and conference budgets
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