JPMorganChase in London seeks an Ultra Low Latency C++ Lead Software Engineer within the Electronic Trading Technology team to design, build, and operate market gateway solutions with FPGA acceleration. You will collaborate with hardware and software teams to achieve deterministic performance and high reliability in production trading systems.
Responsibilities include leading latency optimization, developing across Unix/Linux, and ensuring observability and resiliency.
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This role, Ultra-Low Latency C++ Engineer with FPGA Trading at Testing Site - JPMC, could be your next move.
This opportunity is part of our work in IT & Technology.
The advertised compensation is 120.000 - 180.000.
We aim to respond to suitable candidates as soon as possible.
Full responsibilities and requirements are described in the listing above.
Learn more about the Ultra-Low Latency C++ Engineer with FPGA Trading role in the description above.