Hybrid · Hammersmith, London (United Kingdom)
Job type
Full-time
Department
Pay
Shift/Schedule
Monday - Friday, Hybrid 50% in office
Role
As a Senior Digital Verification Engineer at MintNeuro, you will lead and take ownership of the verification of the digital subsystem in our next-generation mixed-signal ASICs ("Big A, Little D"). In our implantable neural interfaces, the digital subsystem orchestrates, controls and monitors ultra-low-power analog sensors and stimulation engines, so getting it right first time is critical to patient safety and to every tape-out.
We are seeking an engineer who excels at building robust, scalable verification environments and who takes pride in finding bugs before silicon does. You will define how we verify our designs, from block level through to mixed-signal system level, and drive verification closure through to tape-out and lab bring-up in a collaborative, fast-paced R&D team. Experience in RTL design or backend flows is welcome but secondary — verification is the heart of this role.
Duties and Responsibilities
A. Verification Strategy and Planning
- Own the digital verification strategy for our mixed-signal ASICs, from block level to full-chip, and define what "done" looks like for each tape-out.
- Write and maintain verification plans traceable to specifications, requirements & identified hazards.
- Define and track coverage goals (functional, code & assertion) and drive verification sign-off.
B. Testbench Development and Execution
- Design & build reusable, self-checking SystemVerilog testbenches (UVM or equivalent structured methodology), including stimulus generators, reference models, scoreboards and protocol checkers.
- Develop SystemVerilog Assertions (SVA) and apply formal verification where it adds value (e.g. FSMs, safety mechanisms, register access, CDC).
- Run regressions, triage failures, and work with designers to debug and close issues.
- Build and maintain regression infrastructure and automation (scripting, CI, results dashboards).
- Document the verification environment, test cases and results clearly, so they can be reused, reviewed and audited.
C. Mixed-Signal and Safety Verification
- Work with analog IC designers to verify mixed-signal boundaries — control register maps, clocking, power sequencing and analog calibration/trim — using real-number / behavioural models (e.g. SV-RNM, Verilog-AMS) and co-simulation where needed.
- Verify functional safety and fault-tolerance mechanisms (e.g. state machine protection, parity/CRC, watchdogs, reset monitoring), including fault-injection testing.
- Support product risk-management activities (hazard analysis, FMEA/FMEDA), providing verification evidence for design reviews and regulatory documentation.
D. Silicon Bring-up and Collaboration
- Support silicon bring-up, bench testing and validation, correlating lab results with pre-silicon verification and feeding learnings back into the verification flow.
- Support gate-level simulation and pre-silicon validation (FPGA-based emulation where beneficial).
- Work closely with the wider engineering team spanning digital and analog design, system hardware and software/firmware, and produce clear verification plans, reports and review records.
- Provide technical leadership: mentor other engineers, lead verification and design reviews, and help shape our verification methodology and tools as the team grows.
Qualifications
7+ years experience
- A degree, or equivalent practical experience, in Electrical/Electronic Engineering, Computer Engineering, or a related discipline.
- Strong track record in digital ASIC verification, including taking verification of a block or subsystem through to tape-out sign-off.
- Experience using SystemVerilog for verification: building structured, self-checking testbenches (UVM or equivalent), constrained-random stimulus, assertions (SVA) and functional coverage.
- Experience writing verification plans and driving coverage closure.
- Strong debugging skills and the ability to read and reason about RTL (Verilog/SystemVerilog) written by others.
- Scripting skills (e.g. Python, Tcl, shell) for regression automation and results analysis.
- Hands-on experience with industry-standard simulation and verification tools (e.g. Cadence Xcelium, Synopsys VCS or Siemens Questa) and coverage management.
- Experience with version control and issue tracking (e.g. Git, Jira) in a team environment.
- Strong collaborative and communication skills, with the motivation to thrive in an agile, fast-paced startup environment.
Greatly Beneficial
- Safety-Critical Verification: Experience verifying safety-critical or high-reliability systems — especially under standards such as ISO 26262 (automotive), IEC 61508 (industrial), or medical device standards (ISO 13485 / IEC 60601 / IEC 62304) — including fault injection and requirements traceability.
- Mixed-Signal Verification: Experience with real-number modelling, analog behavioural models, or AMS co-simulation, and with verifying analog control/calibration logic.
- Formal Verification: Hands-on use of formal property checking, and/or structural checks such as CDC/RDC and lint.
- Low-Power Verification: Experience verifying power management/sequencing, clock gating or multi-domain designs (e.g. UPF-aware simulation).
Bonus / Nice-to-Have
- RTL Design: Experience writing synthesisable Verilog/SystemVerilog RTL for digital control, serial interfaces or register banks.
- Backend Experience: Familiarity with synthesis, timing constraints (SDC)/STA, DFT/scan insertion or place-and-route — either hands-on or working with outsourced backend partners.
- Hardware/Software Co-verification: Experience verifying designs that include an embedded processor (e.g. RISC-V or Arm) alongside firmware.
- Open-Source Flows: Familiarity with open-source verification tools such as cocotb or Verilator.
- IP blocks: Experience working with SRAM, fuse and OTP memory IPs.
What We Offer
- Work Environment: Dynamic, innovative, and inclusive workplace culture.
- Location Perks: Modern offices and labs located in the heart of London.
- Flexible Working: Hybrid model, allowing up to 50% remote work.
- Compensation: Competitive salary with a comprehensive benefits package.
- Career Development: Work closely with experienced leadership in a high-growth startup with clear development paths.
- Purpose: Be part of a mission-driven team dedicated to making a positive impact on millions of lives worldwide.
- Private Healthcare, Dental and Optical cover.
- 33 days annual leave (including bank holidays).
- Socials, team building and Company days.
We recognise that expertise comes in many forms and that passion drives progress. Even if your experience doesn't perfectly align with every qualification in this job description, we encourage you to apply. We value a diverse range of perspectives and foster an inclusive environment, which opens doors for individuals committed to making an impact in our industry.
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