Infoplus Technologies UK Limited is seeking experienced SoC Design Verification (DV) Engineers to verify a next-generation multi-die SoC using SystemVerilog/UVM. Strong debugging skills and C-based test development are essential as embedded cores are used for processor-driven verification.
Role involves subsystem- and SoC-level verification, regression execution, and collaboration with verification planning.
#J-18808-Ljbffr
Are you ready to take on the Senior SoC Verification Engineer — UVM & SystemVerilog role at Infoplus Technologies UK Limited?
We invite applications for the Senior SoC Verification Engineer — UVM & SystemVerilog position located in Cambridge, England, United Kingdom.
The following opportunity is for a Senior SoC Verification Engineer — UVM & SystemVerilog with Infoplus Technologies UK Limited.
Our organisation is growing, and we are hiring a Senior SoC Verification Engineer — UVM & SystemVerilog in Cambridge, England, United Kingdom.