SiFive, Inc. in Cambridge, UK seeks a Senior RTL Design Engineer to architect and implement new features for RISC-V CPU frontends.
You will integrate content into the Chisel/FIRRTL framework and support automatic configuration, docs, and robust verification. You will verify designs in sandbox environments, collaborate with physical implementation to meet frequency and power goals, and work with performance modeling for optimization.
#J-18808-Ljbffr
This opportunity is for the Senior RTL Engineer - CPU Frontend (RISC-V) role at SiFive, Inc.
This posting is for the Senior RTL Engineer - CPU Frontend (RISC-V) role at SiFive, Inc., based in Cambridge, England, United Kingdom.
We are looking to fill the Senior RTL Engineer - CPU Frontend (RISC-V) position at SiFive, Inc. in Cambridge, England, United Kingdom.
The Senior RTL Engineer - CPU Frontend (RISC-V) role at SiFive, Inc. is now open for applications in Cambridge, England, United Kingdom.