Quant Capital is partnering with a leading trading firm to hire ASIC/FPGA engineers for its ultra-low latency hardware team in London. You will own physical design and verification, shaping floorplanning, place-and-route, timing closure and power analysis for demanding trading applications.
The role suits engineers who started in RTL design and moved into physical implementation, with 4+ years in RTL and verification and experience using Synopsys or Cadence tools.
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For the Low-Latency ASIC Engineer – Physical Design & Verification position at Quant Capital, we are reviewing applications now.
This role, Low-Latency ASIC Engineer – Physical Design & Verification at Quant Capital, could be your next move.
Are you ready to take on the Low-Latency ASIC Engineer – Physical Design & Verification role at Quant Capital?
We would love to welcome a new Low-Latency ASIC Engineer – Physical Design & Verification to our group in Greater London, England, United Kingdom.