Kandou is seeking an Analog Layout Engineer (Lead) to drive custom analog layout and verification for high-speed SerDes and memory interfaces across 28nm to 7nm nodes. You will collaborate with design teams to implement robust layouts, ensure IP and chip integration, and engage with customers on requirements and IP delivery.
The role demands hands-on experience in analog layout and strong communication skills in a fast-paced semiconductor environment. EU/CH/UK location flexibility is offered.
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We invite applications for the Lead Analog Layout Engineer for High-Speed AI Interconnects position located in Reading, England, United Kingdom.
The position is based in Reading, England, United Kingdom.
This opportunity is part of our work in Engineering.
The advertised compensation is 83.000 - 129.000.
We aim to respond to suitable candidates as soon as possible.
Full responsibilities and requirements are described in the listing above.